HDL Design and Simulation
Aldec Active-HDL
Windows® based, Integrated Design Environment (
IDE
) includes full
HDL
and graphical design tool suite and
RTL
/gate-level mixed-language simulator for rapid deployment and verification of
FPGA
designs.
Active-HDL Lattice Edition
Getting Started with Active-HDL
HDL Debugging in Active-HDL
How to Simulate Designs in Active-HDL
