====== HDL Design and Simulation ======

  * **[[https://www.aldec.com/en/products/fpga_simulation/active-hdl|Aldec Active-HDL]]**\\ Windows® based, Integrated Design Environment (IDE) includes full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.\\ {{:soft:commercial.png?nolink}}{{:soft:closed.png?nolink}}{{:soft:winxp.png?nolink}}{{:soft:wine.png?nolink}}
    * <wrap info>[[https://www.aldec.com/en/support/resources/documentation/faq/1746|Active-HDL Lattice Edition]]</wrap>
    * <wrap info>[[https://www.aldec.com/en/support/resources/documentation/articles/1054|Getting Started with Active-HDL]]</wrap>
    * <wrap info>[[https://www.aldec.com/en/support/resources/documentation/articles/1057|HDL Debugging in Active-HDL]]</wrap>
    * <wrap info>[[https://www.aldec.com/en/support/resources/documentation/articles/1060|How to Simulate Designs in Active-HDL]]</wrap>